With rapid development on the integrated circuit (IC) manufacturing technology, size of semiconductors in ICs, especially the size of the MOS (Metal-Oxide-Semiconductor) devices, continues to shrink in order to meet the requirements for the miniaturization and high-degree-integration circuits. As the size of the MOS transistor devices decreases continuously, the existing fabrication technology, which uses silicon oxide or silicon oxynitride as the gate dielectric layer, has been challenged. More particularly, transistors with silicon oxide or silicon oxynitride based gate dielectric layer may have certain problems, such as increased leakage current and impurity diffusion, which may affects the threshold voltage of the transistors. Thus, the performance of semiconductor devices based on such transistors may be impacted.
To solve these problems, transistors with high-K (dielectric constant)/metal gate structures have been introduced. By replacing the silicon oxide or silicon oxynitride gate dielectric materials with the high-K materials, the leakage current can be reduced while the size of the semiconductor devices decreases, and the performance of the semiconductor devices can be improved. Conventional SiO2/poly silicon gate structures of complementary metal-oxide-semiconductor (CMOS) devices have been replaced by the high-K/metal gate structure since 45 nm technology node was used.
An atomic layer deposition (ALD) process is a common method for forming high-K dielectric layers. However, in respect the current ALD process for forming the high-K dielectric layers, the surface of the high-K dielectric layers formed by the ALD process may be rough, thus the performance of the transistors with these high-K dielectric layers may be impacted. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.